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STR73xF
ARM7TDMITM 32-BIT MCU WITH FLASH, 3x CAN, 4 UARTs, 20 TIMERS, ADC, 12 COMM. INTERFACES
DATA BRIEF

Core - ARM7TDMI 32-bit RISC CPU - 32 MIPS @ 36 MHz Temperature Range - Operating temperature range -40 to 105 C Memories - Up to 256 Kbytes FLASH program memory (10,000 cycles endurance, data retention 20 years at 55C) - 16 Kbytes RAM Clock, Reset and Supply Management - 4.5 - 5.5V application supply and I/O interface - Embedded 1.8V regulator for core supply - Embedded oscillator running from external 4-8MHz crystal or ceramic resonator - Up to 36 MHz CPU freq. with internal PLL - Internal RC oscillator 32kHz or 2MHz software configurable for fast startup and backup clock - Realtime Clock for clock-calendar function - Wakeup Timer driven by internal RC for wakeup from STOP mode - 5 power saving modes: SLOW, WAIT, LPWAIT, STOP and HALT modes Nested interrupt controller - Fast interrupt handling with multiple vectors - 64 maskable IRQ with 64 vectors and 16 priority levels - 2 maskable FIQ sources - 16 external interrupts and up to 32 wake up lines Up to 112 I/O ports - 72/112 multifunctional bidirectional I/O lines
TQFP100 14 x 14 TQFP144 20 x 20 LFBGA144 10 x 10 x 1.7

DMA - 4 DMA controllers with 4 channels each Timers - 16-bit watchdog timer (WDG) - 6/10 16-bit timers (TIM) each with: 2 input captures, 2 output compares, PWM and pulse counter modes - 6 16-bit PWM modules (PWM) - 3 16-bit timebase timers with 8-bit prescalers 12 Communications Interfaces - 2 I2C interfaces - 4 UART asynchronous serial communications interfaces - 3 BSPI synchronous serial interfaces - Up to 3 CAN interfaces (2.0B Active) 10-bit A/D Converter - 12/16 channels - Conversion time: min 3s, range: 0 to 5V Development Tools Support - JTAG interface
Table 1. Device Summary
Features FLASH memory - bytes RAM - bytes Peripheral Functions CAN Peripherals Operating Voltage Operating Temperature Packages T=TQFP144 20 x 20 H=LFBGA144 10 x10 STR730FZx 128K 256K STR735FZx 128K 256K 64K STR731FVx 128K 256K 16K 6 TIM Timers, 72 I/Os, 18 Wake-Up lines, 12 ADC channels 3 4.5 to 5.5V (optional 1.8V for core) -40 to +105C T=TQFP100 14x14 0 64K STR736FVx 128K 256K
16K 10 TIM Timers, 112 I/Os, 32 Wake-Up lines, 16 ADC channels 3 0
Rev. 1
July 2005
This is preliminary information on a new product now in development. Details are subject to change without notice.
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1
STR73xF Data Brief
1 INTRODUCTION
This Data Brief provides the STR73xF feature summary, pin description and ordering Information. For complete information on the Mechanical and Electrical Device Characteristics please refer to the Preliminary Datasheet. For complete information on the STR73xF Microcontroller memory, registers and peripherals. please refer to the STR73x Reference Manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference Manual. 1.1 Overview ARM core with embedded Flash & RAM STR73xF family combines the high performance ARM7TDMITM CPU with an extensive range of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed single voltage FLASH memory and high-speed RAM. The STR73xF family has an embedded ARM core and is therefore compatible with all ARM tools and software. Extensive tools support STMicroelectronics' 32-bit, ARM core-based microcontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. This extensive line of hardware/software tools includes starter kits and complete development packages all tailored for ST's ARM core-based MCUs. The range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a JTAG application interface. These support a range of embedded operating systems (OS), while several royalty-free OSs are also available. For more information, please refer to ST MCU site http://www.st.com/mcu Figure 1 shows the general block diagram of the device family. Package Choice: Reduced Pin-Count TQFP100 or Feature-Rich 144-pin TQFP or LFBGA The STR73xF family is available in 3 packages. The TQFP144 and LFBGA144 versions have the full set of all features. The 100-pin version has fewer timers, I/Os and ADC channels. Refer to the Device Summary on Page 1 for a comparison of the I/Os available on each package. The family includes versions with and without CAN.
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1
STR73xF Data Brief High Speed Flash Memory The Flash program memory is organized in 32-bit wide memory cells which can be used for storing both code and data constants. It is accessed by CPU with zero wait states @ 36 MHz. The STR7 embedded Flash memory can be programmed using In-Circuit Programming or In-Application programming. The Flash memory endurance is 10K write/erase cycles and the data retention is 20 years at 55C. IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board. The Flash memory can be protected against different types of unwanted access (read/write/ erase). There are two types of protection:
* *
Sector Write Protection Flash Debug Protection (locks JTAG access)
Flexible Power Management To minimize power consumption, you can program the STR73xF to switch to SLOW, WAIT LPWAIT, STOP or HALT modes depending on the current system activity in the application. Flexible Clock Control Two clock sources are used to drive the microcontroller, a main clock driven by an external crystal or ceramic resonator and an internal backup RC oscillator that operates at 2MHz or 32 kHz. The embedded PLL allows the internal system clock (up to 36 MHz) to be generated from a main clock frequency of 10 MHz or less. The PLL output frequency can be programmed using a wide selection of multipliers and dividers. Voltage Regulators The STR73xF requires an external 4.5 to 5.5V power supply. There are two internal Voltage Regulators for generating the 1.8V power supply needed by the core and peripherals. The main VR is switched off and the Low Power VR switched on when the application puts the STR73xF in Low Power Wait (LPWAIT) mode.
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STR73xF Data Brief Low Voltage Detectors The voltage regulator and Flash modules each have an embedded LVD that monitors the internal 1.8V supply. If the voltage drops below a certain threshold, the LVD will reset the STR73xF. Note: An external power-on reset must be provided ensure the microcontroller starts-up correctly. On-Chip Peripherals CAN Interfaces The three CAN modules are compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed up to 1 MBaud. These are not available in the STR735 and STR736. DMA 4 DMA controllers, each with 4 data streams manage memory to memory, peripheral to memory and memory to peripheral transfers. The DMA requests are connected to TIM timers, BSPI0, BSPI1, BSPI2 and ADC. One of the streams can be configured to be triggered by a software request, independently from any peripheral activity. 16-bit Timers (TIM) Each of the ten timers (six in 100-pin devices) have a 16-bit free-running counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. This provides a total of 16 independent PWMs (12 in 100-pin devices) when added with the PWM modules (see next paragraph). PWM Modules (PWM) The six 16-bit PWM modules have independently programmable periods and duty-cycles, with 5+3 bit prescaler factor. Timebase Timers (TB) The three 16-bit Timebase Timers with 8-bit prescaler for general purpose time triggering operations. Realtime Clock (RTC) The RTC provides a set of continuously running counters driven by separate clock signal derived from the main oscillator. The RTC can be used as a general timebase or clock/ calendar/alarm function. When the STR73xF is in LPWFI mode the RTC keeps running, powered by the low power voltage regulator. UARTs The 4 UARTs allow full duplex, asynchronous, communications with external devices with independently programmable TX and RX baud rates up to 625K baud.
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STR73xF Data Brief Buffered Serial Peripheral Interfaces (BSPI) Each of the three BSPIs allow full duplex, synchronous communications with external devices, master or slave communication at up 6 Mb/s (@36 MHz System Clock). I2C Interfaces The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 kHz) and 7 or 10-bit addressing modes. A/D Converter The 10-bit Analog to Digital Converter, converts up to 16 channels in single-shot or continuous conversion modes (12 channels in 100-pin devices). The minimum conversion time is 3us. Watchdog The 16-bit Watchdog Timer protects the application against hardware or software failures and ensures recovery by generating a reset. I/O Ports Up to 112 I/O ports (72 in 100-pin devices) are programmable as general purpose input/ output or Alternate Function. External Interrupts and Wake-Up Lines 16 external interrupts lines are available for application use. In addition, up to 32 external Wakeup lines (18 in 100-pin devices) can be used as general purpose interrupts or to wake-up the application from STOP mode.
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STR73xF Data Brief Figure 1. STR730F/STR735F Block Diagram
RSTIN PRCCU/PLL
ARM7TDMI CPU
ARM7 NATIVE BUS
FLASH Program Memory 64/128/256K RAM 16K APB BRIDGE 0 APB BRIDGE 1
M0 M1 TEST
JTDI JTCK JTMS JTRST JTDO V18 VDD VSS VDDA VSSA
JTAG
POWER SUPPLY VREG AHB BRIDGE
AHB BUS
DMA0-3 CLOCK MGT (CMU) XTAL1 XTAL2 OSC RTC WATCHDOG I2C0-1 WAKEUP/INT (WIU) UART0, 1, 2, 3
APB BUS APB BUS
4 AF 32 AF 8 AF
INTERRUPT CTL (EIC) 16 AF 12 AF 12 AF 6 AF 6 AF 122 ports A/D CONVERTER (ADC) TIMER (TIM) 2-4 BSPI 0-2 CAN 0-2* PWM 0-5 GPIO PORTS 0-6
TIMEBASE TIMER (TB) 0-2 WAKEUP TIMER (WUT) TIMER (TIM) 0-1 TIMER (TIM) 5-9 8 AF 20 AF
*CAN peripherals not available on STR735F.
AF: alternate function on I/O port pin
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STR73xF Data Brief Figure 2. STR731F/STR736 Device Block Diagram
RSTIN PRCCU/PLL
ARM7TDMI CPU
ARM7 NATIVE BUS
FLASH Program Memory 64/128/256K RAM 16K APB BRIDGE 0 APB BRIDGE 1
M0 M1 TEST
JTDI JTCK JTMS JTRST JTDO V18 VDD VSS VDDA VSSA
JTAG
POWER SUPPLY VREG AHB BRIDGE
AHB BUS
DMA0-3 CLOCK MGT (CMU) XTAL1 XTAL2 OSC RTC WATCHDOG I2C0-1 WAKEUP/INT (WIU) UART0, 1, 2, 3
APB BUS APB BUS
4 AF 18 AF 8 AF
INTERRUPT CTL (EIC) 12 AF 12 AF 12 AF 6 AF 6 AF 72 ports A/D CONVERTER (ADC) TIMER (TIM) 2-4 BSPI 0-2 CAN 0-2* PWM 0-5 GPIO PORTS 0-6
TIMEBASE TIMER (TB) 0-2 WAKEUP TIMER (WUT) TIMER (TIM) 0-1 TIMER (TIM) 5 8 AF 4 AF
*CAN peripherals not available on STR736F.
AF: alternate function on I/O port pin
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STR73xF Data Brief 1.2 Related Documentation Available from www.arm.com: ARM7TDMI Technical Reference Manual Available from http://www.st.com: STR7 Flash Programming Reference Manual STR73x Software Library User Manual For a list of related application notes refer to http://www.st.com.
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STR73xF Data Brief 1.3 Pin Description 1.3.1 STR730F/STR735F (TQFP144)
Figure 3. STR730F/STR735F Pin Configuration (top view)
OCMPB2 / P0.0 OCMPA2 / P0.1 ICAPA2 / P0.2 ICAPB2 / P0.3 VSS VDD OCMPA5 / P0.4 OCMPB5 / P0.5 ICAPA5 / P0.6 ICAPB5 / P0.7 OCMPA6 / P0.8 OCMPB6 / P0.9 OCMPA7 / P0.10 OCMPB7 / P0.11 VDD VSS ICAPA3 / P0.12 ICAPB3 / P0.13 OCMPB3 / P0.14 OCMPA3 / P0.15 OCMPA4 / P1.0 OCMPB4 / P1.1 ICAPB4 / P1.2 ICAPA4 / P1.3 VSS VDD P1.4 P1.5 OCMPB1 / P1.6 OCMPA1 / P1.7 INT0 / OCMPA0 / P1.8 INT1 / OCMPB0 / P1.9 ICAPB0 / WUP28 / P1.10 ICAPA0 / WUP29 / P1.11 ICAPA1 / WUP30 / P1.12 ICAPB1 / WUP31 / P1.13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
P6.15 / WUP9 P6.14 / SS0 P6.13 / SCK0 / WUP11 P6.12 / MOSI0 P6.11 / MISO0 P6.10 / WUP8 P6.9 / TDO0 P6.8 / RDI0 / WUP10 P6.7 / WUP7 P6.6 / WUP6 P6.5 / WUP5 P6.4 / TDO3 / WUP4 P6.3 / WUP3 P6.2 / RDI3 / WUP2 P6.1 / WUP1 P6.0 / WUP0 VDD VSS V18 P5.15 / INT13 P5.14 / INT12 P5.13 / INT11 P5.12 / INT10 P5.11 / TDO2 / INT9 P5.10 / RDI2 / INT8 P5.9 / INT7 P5.8 / INT6 P5.7 / MISO2 P5.6 / MOSI2 P5.5 / SCK2 / WUP23 P5.4 / SS2 P5.3 / OCMPB9 P5.2 / OCMPA9 P5.1 / MISO1 P5.0 / MOSI1 P4.15 / SCK1 / WUP22
STR730F/STR735F
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
P4.14 / SS1 P4.13 / ICAPB9 P4.12 / ICAPA9 / WUP21 P4.11 / OCMPB8 P4.10 / ICAPA6 / WUP20 P4.9 / ICAPB6 P4.8 / OCMPA8 P4.7 / SDA1 P4.6 / SCL1 / WUP19 P4.5 / CAN2RX / WUP18 P4.4 / CAN2TX P4.3 / ICAPB8 / WUP27 P4.2 / ICAPA8 / WUP26 P4.1 / ICAPB7 / WUP25 P4.0 / ICAPA7 / WUP24 VDD VSS JTDO JTCK JTMS JTDI JTRST VSS VDD P3.15 / AIN15 / INT5 P3.14 / AIN14 / INT4 P3.13 / AIN13 / INT3 P3.12 / AIN12 / INT2 P3.11 / AIN11 P3.10 / AIN10 P3.9 / AIN9 P3.8 / AIN8 VDDA VSSA P3.7 / AIN7 P3.6 / AIN6
Note 1: CAN alternate functions not available on STR735F.
WUP12 / CAN0RX / P1.14 CAN0TX / P1.15 PWM0 / P2.0 WUP13 / CAN1RX / P2.1 CAN1TX / P2.2 PWM1 / P2.3 PWM2 / P2.4 PWM3 / P2.5 PWM4 / P2.6 PWM5 / P2.7 M0 RSTIN M1 VDD VSS XTAL1 XTAL2 VSS TDO1 / P2.8 WUP14 / RDI1 / P2.9 WUP16 / P2.10 WUP17 / P2.11 INT14 / P2.12 INT15 / P2.13 WUP15 / SCL0 / P2.14 SDA0 / P2.15 TEST VBIAS VSS VDD AIN0 / P3.0 AIN1 / P3.1 AIN2 / P3.2 AIN3 / P3.3 AIN4 / P3.4 AIN5 / P3.5
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
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STR73xF Data Brief 1.3.2 STR730F/STR735F (LFBGA144)
Table 2. STR730F/STR735F LFBGA Ball Connections
Ball
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
Name
P0.0 / OCMPB2 P6.10 / WUP8 P6.9 / TDO0 P6.12 / MOSI0 P6.6 / WUP6 V18 P5.15 / INT13 P5.8 / INT6 P5.2 / OCMPA9 P5.7 / MISO2 P5.6 / MOSI2 P5.11 / TDO2 / INT9
Ball
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12
Name
P0.4 / OCMPA5 P0.1 / OCMPA2 P6.15 / WUP9 P6.13 / SCKO / WUP11 P6.7 / WUP7 P6.2 / WUP2 / RDI3 P5.14 / INT12 P5.9 / INT7 P5.3 / OCMPB9 P5.0 / MOSI1 P4.15 / SCK1 / WUP22 P4.8 / OCMPA8
Ball
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12
Name
P0.5 / OCMPB5 P0.2 / ICAPA2 P0.3 / ICAPB2 P6.14 / SSO P6.8 / RDI0 / WUP10 P6.3 / WUP3 VSS P5.10 / INT8 / RDI2 P5.4 / SS2 P5.1 / MISO1 P4.14 / SS1 P4.7 / SDA1
Ball
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12
Name
VSS VDD P0.6 / ICAPA5 P0.7 /ICAPB5 P6.11 / MISO0 P6.4 / WUP4 /TDO3 VDD P5.12 / INT10 P5.5 / SCK2 / WUP23 P4.13 / ICAPB9 P4.12 / ICAPA9 / WUP21 P4.11 / OCMPB8
E1 E2 E3 E4 E5 E6 E7 E8 E9
P0.8 / OCMPA6 P0.9 / OCMPB6 P0.10 / OCMPA7 P0.11 / OCMPB7 P0.12 / ICAPA3 P6.5 / WUP5 P6.0 / WUP0 P5.13 / INT11 P4.10 / ICAPA6 / WUP20
F1 F2 F3 F4 F5 F6 F7 F8 F9
VDD P0.13 / ICAPB3 P0.14 / OCMPB3 P0.15 / OCMPA3 P1.0 / OCMPA4 P1.1 / OCMPB4 P6.1 / WUP1 P4.4 / CAN2TX1)
G1 G2 G3 G4 G5 G6 G7 G8 G9
VSS P1.2 / ICAPB4 P1.3 / ICAPA4 VSS P1.5 P2.11 / WUP17 P4.0 / ICAPA7 / WUP24 VDD VSS
H1 H2 H3 H4 H5 H6 H7 H8 H9
VDD P1.8 / OCMPA0 / INT0 P1.9 / OCMPB0 / INT1 P1.10 / ICAPB0 / WUP28 XTAL2 P2.10 / WUP16 P2.15 / SDA 0 JTMS VSS
P4.3 / ICAPB8 / WUP27
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STR73xF Data Brief Table 2. STR730F/STR735F LFBGA Ball Connections
Ball
E10 E11 E12
Name
P4.9 / ICAPB6 P4.6 / SCL1 / WUP19 P4.5 / WUP18 / CAN2RX 1)
Ball
F10 F11 F12
Name
P4.2 / ICAPA8 / WUP26 P4.1 / ICAPB7 / WUP25 JTDI
Ball
G10 G11 G12
Name
JTDO JTCK nJTRST
Ball
H10 H11 H12
Name
VDD P3.15 / AIN15 / INT5 P3.14 / AIN14 / INT4
J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12
P1.4 P1.11 / ICAPA0 / WUP29 P1.12 / ICAPA1 / WUP30 P2.7 / PWM5 VDD P2.9 / RDI1 / WUP14 P2.14 / SCL 0 / WUP15 P3.1 / AIN1 P3.13 / AIN13 / INT3 P3.12 / AIN12 / INT2 P3.9 / AIN9 P3.8 / AIN8
K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12
P1.6 / OCMPB1 P1.13 / ICAPB1 / WUP31 P2.1 / WUP13 CAN1RX1) /
L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12
P1.7 / OCMPA1 P1.15 / CAN0TX1) P2.0 / PWM0 P2.3 / PWM1 RSTIN VSS P2.12 / INT14 VBIAS P3.3 / AIN3 P3.5 / AIN5 P3.7 / AIN7 P3.10 / AIN10
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12
P1.14 / CAN0RX 1) / WUP12 P2.4 / PWM2 P2.5 / PWM3 P2.2 / CAN1TX1) M0 VSS XTAL1 TST P3.2 / AIN2 VSS VDD P3.6 / AIN6
P2.6 / PWM4 M1 P2.8 / TDO1 P2.13 / INT15 P3.0 / AIN0 P3.4 / AIN4 VDDA VSSA P3.11 / AIN11
Note 1: CAN alternate functions not available on STR735F.
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STR73xF Data Brief 1.3.3 STR731F/STR736F (TQFP100)
Figure 4. STR731F/STR736F Pin Configuration (top view)
OCMPB2 / P0.0 OCMPA2 / P0.1 ICAPA2 / P0.2 ICAPB2 / P0.3 OCMPA5 / P0.4 OCMPB5 / P0.5 ICAPA5 / P0.6 VDD VSS ICAPA3 / P0.12 ICAPB3 / P0.13 OCMPB3 / P0.14 OCMPA3 / P0.15 OCMPA4 / P1.0 OCMPB4 / P1.1 ICAPB4 / P1.2 ICAPA4 / P1.3 OCMPB1 / P1.6 OCMPA1 / P1.7 INT0 / OCMPA0 / P1.8 INT1 / OCMPB0 / P1.9 ICAPB0 / WUP28 / P1.10 ICAPA0 / WUP29 / P1.11 ICAPA1 / WUP30 / P1.12 ICAPB1 / WUP31 / P1.13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P6.14 / SS0 P6.13 / SCK0 / WUP11 P6.12 / MOSI0 P6.11 / MISO0 P6.9 / TDO0 P6.8 / RDI0 / WUP10 P6.6 / WUP6 P6.4 / TDO3 / WUP4 P6.2 / RDI3 / WUP2 P6.0 / WUP0 VDD VSS V18 P5.12 / INT10 P5.11 / TDO2 / INT9 P5.10 / RDI2 / INT8 P5.9 / PWM5 / INT7 P5.8 / PWM4 / INT6 P5.7 / MISO2 P5.6 / MOSI2 P5.5 / SCK2 / WUP23 P5.4 / SS2 /PWM3 P5.1 / MISO1 P5.0 / MOSI1 P4.15 / SCK1 / WUP22
STR731F/STR736F
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P4.14 / SS1 P4.10 / ICAPB5 / WUP20 P4.7 / SDA1 P4.6 / SCL1 / WUP19 VDD VSS JTDO JTCK JTMS JTDI JTRST VSS VDD P3.15 / AIN11 / INT5 P3.14 / AIN10 / INT4 P3.13 / AIN9 / INT3 P3.12 / AIN8 / INT2 P3.11 / AIN7 P3.10 / AIN6 P3.9 / AIN5 P3.8 / AIN4 VDDA VSSA P3.7 / AIN3 P3.6 / AIN2
Note 1: CAN alternate functions not available on STR736F.
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WUP12 / CAN0RX / P1.14 CAN0TX / P1.15 PWM0 / P2.0 WUP13 / CAN1RX / P2.1 CAN1TX / P2.2 PWM1 / P2.3 PWM2 / P2.4 M0 RSTIN M1 VDD VSS XTAL1 XTAL2 VSS CAN2RX / TDO1 / P2.8 WUP14 / CAN2TX / RDI1 / P2.9 WUP15 / SCL0 / P2.14 SDA0 / P2.15 TEST VBIAS VSS VDD AIN0 / P3.4 AIN1 / P3.5
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
STR73xF Data Brief
Legend / Abbreviations for Table 3: Type: I = input, O = output, S = supply, HiZ= high impedance, In/Output level: TT= TTL 0.8V / 2V with input trigger CT= CMOS 0.3VDD/0.7VDD with input trigger Port and control configuration: - Input: pu/pd = with internal 100k weak pull-up or pull down - Output: OD = open drain (logic level) PP = push-pull Interrupts: INTx =external interrupt line WUPx =Wake-Up interrupt line The reset state of the I/O ports is input floating. To avoid excess power consumption, unused I/O ports must be tied to ground.
Table 3. STR73xF Pin Description
Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name Input interrupt pu/pd Output Capability Main function (after reset) Alternate function
OD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
A1 B2 C2 C3 D1 D2 B1 C1 D3 D4 E1 E2 E3 E4 F1 G1 E5 F2 F3
1 2 3 4
P0.0/OCMPB2 P0.1/OCMPA2 P0.2/ICAPA2 P0.3/ICAPB2 VSS VDD
I/O TT I/O TT I/O TT I/O TT S S I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT
2mA X 2mA X 2mA X 2mA X
PP X X X X X X X X X X X X
Port 0.0 TIM2: Output Compare B output Port 0.1 TIM2: Output Compare A output Port 0.2 TIM2: Input Capture A input Port 0.3 TIM2: Input Capture B input Ground for digital I/O (5V) Supply voltage for digital I/O (5V)
5 6 7
P0.4/OCMPA5 P0.5/OCMPB5 P0.6/ICAPA5 P0.7/ICAPB5 P0.8/OCMPA6 P0.9/OCMPB6
2mA X 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X
Port 0.4 TIM5: Output Compare A output Port 0.5 TIM5: Output Compare B output Port 0.6 TIM5: Input Capture A input Port 0.7 TIM5: Input Capture B input Port 0.8 TIM6: Output Compare A output Port 0.9 TIM6: Output Compare B output Port 0.10 Port 0.11 TIM7: Output Compare A output TIM7: Output Compare B output
P0.10/OCMPA7 I/O TT P0.11/OCMPB7 I/O TT 8 9 10 11 12 VDD VSS P0.12/ICAPA3 P0.13/ICAPB3 S S I/O TT I/O TT
Supply voltage for digital I/O (5V) Ground for digital I/O (5V) 2mA X 2mA X 2mA X X X X Port 0.12 Port 0.13 Port 0.14 TIM3: Input Capture A input TIM3: Input Capture B input TIM3: Output Compare B output
P0.14/OCMPB3 I/O TT
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STR73xF Data Brief Table 3. STR73xF Pin Description
Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name Input interrupt pu/pd Output Capability Main function (after reset) Port 0.15 Alternate function
OD
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
F4 F5 F6 G2 G3 G4 H1 J1 G5 K1 L1 H2 H3 H4 J2 J3 K2 M1 L2 L3 K3 M4 L4 M2 M3 K4 J4 M5 L5 K5 J5
13 14 15 16 17
P0.15/OCMPA3 I/O TT P1.0/OCMPA4 P1.1/OCMPB4 P1.2/ICAPB4 P1.3/ICAPA4 VSS VDD P1.4 P1.5 I/O TT I/O TT I/O TT I/O TT S S I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I I I S INT0 INT1
2mA X 2mA X 2mA X 2mA X 2mA X
PP X X X X X
TIM3: Output Compare A output
Port 1.0 TIM4: Output Compare A output Port 1.1 TIM4: Output Compare B output Port 1.2 TIM4: Input Capture B input Port 1.3 TIM4: Input Capture A input Ground for digital I/O (5V) Supply voltage for digital I/O (5V)
2mA X 2mA X 2mA X 2mA X 2mA X 2mA X
X X X X X X X X X X X X X X X X X X X X
Port 1.4 Port 1.5 Port 1.6 TIM1: Output Compare B output Port 1.7 TIM1: Output Compare A output Port 1.8 TIM0: Output Compare A output Port 1.9 TIM0: Output Compare B output Port 1.10 Port 1.11 Port 1.12 Port 1.13 Port 1.14 Port 1.15 TIM0: Input Capture B input TIM0: Input Capture A input TIM1: Input Capture A input TIM1: Input Capture B input CAN0: Receive Data input CAN0: Transmit Data output
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.6/OCMPB1 P1.7/OCMPA1 P1.8/OCMPA0 P1.9/OCMPB0 P1.10/ICAPB0 P1.11/ICAPA0 P1.12/ICAPA1 P1.13/ICAPB1 P1.14/CAN0RX P1.15/CAN0TX P2.0/PWM0 P2.1/CAN1RX P2.2/CAN1TX P2.3/PWM1 P2.4/PWM2 P2.5/PWM3 P2.6/PWM4 P2.7/PWM5
WUP28 2mA X WUP29 2mA X WUP30 2mA X WUP31 2mA X WUP12 2mA X 2mA X 2mA X WUP13 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X
Port 2.0 PWM0: PWM output Port 2.1 CAN1: Receive Data input Port 2.2 CAN1: Transmit Data output Port 2.3 PWM1: PWM output Port 2.4 PWM2: PWM output Port 2.5 PWM3: PWM output Port 2.6 PWM4: PWM output Port 2.7 PWM5: PWM output BOOT: Mode selection 0 input Reset input BOOT: Mode selection 1 input Supply voltage for digital I/O (5V)
33 34 35 36
M0 RSTIN M1 VDD
TT pd CT pu TT pd
14/22
STR73xF Data Brief Table 3. STR73xF Pin Description
Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name Input interrupt pu/pd Output Capability Main function (after reset) Alternate function
OD
51 52 53 54 55
M6 M7 H5 L6 K6
37 38 39 40 41
VSS XTAL1 XTAL2 VSS P2.8/TDO1/ CAN2RX P2.9/RDI1/ CAN2TX P2.10 P2.11 P2.12 P2.13
S I O S I/O TT 2mA X X
PP
Ground for digital I/O (5V) Oscillator amplifier circuit input and internal clock generator input. Oscillator amplifier circuit output. Ground for digital I/O (5V) Port 2.8 CAN2: Receive UART1: Transmit Data input Data output (TQFP100 only) UART1: Receive Data input CAN2: Transmit Data output (TQFP100 only)
56 57 58 59 60 61 62 63 64
J6 H6 G6 L7 K7 J7 H7 M8 L8
42
I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I S S S I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT pd
WUP14 2mA X WUP16 2mA X WUP17 2mA X INT14 2mA X INT15 2mA X WUP15 2mA X 2mA X
X X X X X X X
Port 2.9 Port 2.10 Port 2.11 Port 2.12 Port 2.13 Port 2.14 Port 2.15
43 44 45 46
P2.14/SCL0 P2.15/SDA0 Test VBIAS VSS VDD P3.0/AIN0 P3.1/AIN1 P3.2/AIN2 P3.3/AIN3
I2C0:Serial Clock I2C0:Serial Data
Reserved pin. Must be tied to ground Internal RC Oscillator bias. A 1.3M external resistor has to be connected to this pin when a 32kHZ RC oscillator frequency is used. Ground for digital I/O (5V) Supply voltage for digital I/O (5V) 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X X X X X X X X X Port 3.0 ADC: Analog input 0 Port 3.1 ADC: Analog input 1 Port 3.2 ADC: Analog input 2 Port 3.3 ADC: Analog input 3 Port 3.4 Port 3.5 Port 3.6 Port 3.7 ADC: Analog input 4 (AIN0 in TQFP100) ADC: Analog input 5 (AIN1 in TQFP100) ADC: Analog input 6 (AIN2 in TQFP100) ADC: Analog input 7 (AIN3 in TQFP100)
65 M10 47 66 M11 48 67 68 69 70 71 K8 J8 M9 L9 K9 49
P3.4/AIN4 P3.5/AIN5 P3.6/AIN6 P3.7/AIN7
72 L10 50 73 M12 51 74 L11 52
15/22
STR73xF Data Brief Table 3. STR73xF Pin Description
Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name Input interrupt pu/pd Output Capability Main function (after reset) Alternate function
OD
75 K11 53 76 K10 54 77 J12 55 78 J11 56 79 L12 57 80 K12 58 81 J10 59 82 J9 60
VSSA VDDA P3.8/AIN8 P3.9/AIN9 P3.10/AIN10 P3.11/AIN11 P3.12/AIN12 P3.13/AIN13 P3.14/AIN14 P3.15/AIN15 VDD VSS JTRST JTDI JTMS JTCK JTDO VSS VDD P4.0/ICAPA7 P4.1/ICAPB7 P4.2/ICAPA8 P4.3/ICAPB8 P4.4/CAN2TX P4.5/CAN2RX P4.6/SCL1 P4.7/SDA1 P4.8/OCMPA8 P4.9/ICAPB6
S S I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT S S I I I I O S S I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT WUP24 2mA X WUP25 2mA X WUP26 2mA X WUP27 2mA X 2mA X WUP18 2mA X WUP19 2mA X 2mA X 2mA X 2mA X X X X X X X X X X X TT INT2 INT3 INT4 INT5 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X X X X X X X X X
PP
Reference ground for A/D converter Reference voltage for A/D converter Port 3.8 Port 3.9 Port 3.10 Port 3.11 Port 3.12 Port 3.13 Port 3.14 Port 3.15 ADC: Analog input 8 (AIN4 in TQFP100) ADC: Analog input 9 (AIN5 in TQFP100) ADC: Analog input 10 (AIN6 in TQFP100) ADC: Analog input 11 (AIN7 in TQFP100) ADC: Analog input 12 (AIN8 in TQFP100) ADC: Analog input 13 (AIN9 in TQFP100) ADC: Analog input 14 (AIN10 in TQFP100) ADC: Analog input 15 (AIN11 in TQFP100)
83 H12 61 84 H11 62 85 H10 63 86 H9 64 87 G12 65 88 F12 66 89 H8 67
Supply voltage for digital I/O (5V) Ground for digital I/O (5V) JTAG Reset Input JTAG Data input JTAG Mode Selection Input JTAG Clock Input 4mA JTAG data output. Note: Reset state = HiZ Ground for digital I/O (5V) Supply voltage for digital I/O (5V) Port 4.0 TIM7: Input Capture A input Port 4.1 TIM7: Input Capture B input Port 4.2 TIM8: Input Capture A input Port 4.3 TIM8: Input Capture B input Port 4.4 CAN2: Transmit Data output Port 4.5 CAN2: Receive Data input Port 4.6 I2C1:Serial Clock Port 4.7 I2C1:Serial Data Port 4.8 TIM8: Output Compare A output Port 4.9 TIM6: Input Capture B input
TT pu TT pu TT pd
90 G11 68 91 G10 69 92 93 94 G9 G8 G7 70 71
95 F11 96 F10 97 98 F9 F8
99 E12 100 E11 72 101 C12 73 102 B12 103 E10
16/22
STR73xF Data Brief Table 3. STR73xF Pin Description
Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name Input interrupt pu/pd Output Capability Main function (after reset) Alternate function
OD
PP
104 E9 105 D12 106 D11 107 D10
74
P4.10/ICAPA6/ ICAPB5
I/O TT
WUP20 2mA X 2mA X WUP21 2mA X 2mA X 2mA X WUP22 2mA X 2mA X 2mA X 2mA X 2mA X 2mA X WUP23 2mA X 2mA X 2mA X INT6 INT7 INT8 INT9 2mA X 2mA X 2mA X 2mA X
X X X X X X X X X X X X X X X X X X X X X X
Port 4.10 Port 4.11 Port 4.12 Port 4.13 Port 4.14 Port 4.15
TIM6: Input TIM5: Input Capture A input Capture B input (144-pin pkg only) (TQFP100 only) TIM8: Output Compare B output TIM9: Input Capture A input TIM9: Input Capture B input BSPI1: Slave Select BSPI1: Serial Clock
P4.11/OCMPB8 I/O TT P4.12/ICAPA9 P4.13/ICAPB9 P4.14/SS1 P4.15/SCK1 P5.0/MOSI1 P5.1/MISO1 P5.2/OCMPA9 P5.3/OCMPB9 79 80 P5.4/SS2/ PWM3 P5.5/SCK2 P5.6/MOSI2 P5.7/MISO2 P5.8/PWM4 P5.9/PWM5 P5.10/RDI2 P5.11/TDO2 P5.12 P5.13 P5.14 P5.15 88 89 90 V18 VSS VDD I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT S S S
108 C11 75 109 B11 76 110 B10 77 111 C10 78 112 A9 113 B9 114 C9 115 D9
Port 5.0 BSPI1: Master Output/Slave input Port 5.1 BSPI1: Master input/Slave output Port 5.2 TIM9: Output Compare A output Port 5.3 TIM9: Output Compare B output Port 5.4 BSPI2: Slave Select PWM3: PWM output (TQFP100 only)
Port 5.5 BSPI2: Serial Clock Port 5.6 BSPI2: Master Output/Slave input Port 5.7 BSPI2: Master input/Slave output Port 5.8 PWM4: PWM output (TQFP100 only) Port 5.9 PWM5: PWM output (TQFP100 only) Port 5.10 Port 5.11 Port 5.12 Port 5.13 Port 5.14 Port 5.15 Supply voltage for core provided by internal voltage regulator Ground for digital I/O (5V) Supply voltage for digital I/O (5V) UART2: Receive Data input UART2: Transmit Data output
116 A11 81 117 A10 82 118 A8 119 B8 120 C8 83 84 85
121 A12 86 122 D8 123 E8 124 B7 125 A7 126 A6 127 C7 128 D7 87
INT10 2mA X INT11 2mA X INT12 2mA X INT13 2mA X
17/22
STR73xF Data Brief Table 3. STR73xF Pin Description
Pin n LFBGA144 Input Level TQFP144 TQFP100 Type Pin Name Input interrupt pu/pd Output Capability Main function (after reset) Port 6.0 Port 6.1 Port 6.2 UART3: Receive Data input Port 6.3 Port 6.4 UART3: Transmit Data output Port 6.5 Port 6.6 Port 6.7 Port 6.8 UART0: Receive Data input Port 6.9 UART0: Transmit Data output Port 6.10 Port 6.11 Port 6.12 Port 6.13 Port 6.14 Port 6.15 BSPI0: Master input/Slave output BSPI0: Master Output/Slave input BSPI0: Serial Clock BSPI0: Slave Select Alternate function
OD
129 E7 130 F7 131 B6 132 C6 133 D6 134 E6 135 A5 136 B5 137 C5 138 A3 139 A2 140 D5 141 A4 142 B4
91
P6.0 P6.1
I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT I/O TT
WUP0 8mA X WUP1 2mA X WUP2 2mA X WUP3 2mA X WUP4 2mA X WUP5 2mA X WUP6 2mA X WUP7 2mA X WUP10 2mA X 2mA X WUP8 2mA X 2mA X 2mA X WUP11 2mA X 2mA X WUP9 2mA X
92
P6.2/RDI3 P6.3
93
P6.4/TDO3 P6.5
94
P6.6 P6.7
95 96
P6.8/RDI0 P6.9/TDO0 P6.10
97 98 99
P6.11/MISO0 P6.12/MOSI0 P6.13/SCK0
143 C4 100 P6.14/SS0 144 B3 P6.15
18/22
PP X X X X X X X X X X X X X X X X
STR73xF Data Brief 1.4 Memory Mapping Figure 5 shows the various memory configurations of the STR73xF system. The system memory map (from 0x0000_0000 to 0xFFFF_FFFF) is shown on the left part of the figure, the right part shows maps of the Flash and APB areas. For flexibility the Flash or RAM addresses can be aliased to Block 0 addresses using the remapping feature Most reserved memory spaces (gray shaded areas in Figure 5) are protected from access by the user code. When an access this memory space is attempted, an ABORT signal is generated. Depending on the type of access, the ARM processor will enter "prefetch abort" state (Exception vector 0x0000_000C) or "data abort" state (Exception vector 0x0000_0010). It is up to the application software to manage these abort exceptions.
19/22
STR73xF Data Brief Figure 5. Memory Map
Addressable Memory Space 4 Gbytes
0xFFFF FFFF 0xFFFF 8000 APB TO ARM7 BRIDGE
APB Memory Space 32 Kbytes
0xFFFF FFFF 0xFFFF FC00 0xFFFF FBFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF F800 F7FF F600 F400 F3FF
32K
EIC ADC CMU RTC DMA 0-3 TIM 4
1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K 1K
7
0xE000 0000 0xDFFF FFFF
FLASH Memory Space 64K/128/256 Kbytes
0x8010 DFFF
0xFFFF F000 0xFFFF EFFF 0xFFFF EC00 0xFFFF EBFF
6
0xC000 0000 0xBFFF FFFF
System Memory Flash registers
0x8010 C000 0x8010 0017 0x8010 0000
8K 20B
TIM 3
0xFFFF E800 0xFFFF E7FF
TIM 2
0xFFFF E400 0xFFFF E3FF 0xFFFF E000 0xFFFF DFFF 0xFFFF DC00 0xFFFF DBFF
BSPI 2 BSPI 1 BSPI 0 GP I/O 0-6 PWM 0-5 CAN 2(4)
5
0xA000 3FFF 0xA000 0000 0x9FFF FFFF RAM
0xFFFF D800 0xFFFF D7FF 0xFFFF D400 0xFFFF D3FF
16K
0xFFFF D000 0xFFFF CFFF 0xFFFF CC00 0xFFFF CBFF
4
0x8010 0017 0x8000 0000 0x7FFF FFFF FLASH
0xFFFF C800 0xFFFF C7FF 0xFFFF C400 0xFFFF C3FF
CAN 1(4) CAN 0(4)
64K/128K/256K
0xFFFF C000 0xFFFF BFFF 0xFFFF BC00 0xFFFF BBFF
APB BRIDGE 1 REGS reserved WAKEUP reserved TIM 5-9 TIM 1 TIM 0 WAKEUPTIM WDG UART 3 UART 1 UART 2 UART 0 TB 0-2
3
0x6000 03FF 0x6000 0000 0x5FFF FFFF PRCCU
0xFFFF B800 0xFFFF B7FF 0xFFFF B400 0xFFFF B3FF
1K
0x8003 FFFF
0xFFFF B000 0xFFFF AFFF
B0F7(2)
64K
0xFFFF AC00 0xFFFF ABFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF A800 A7FF A600 A400 A3FF A200 A000 9FFF 9E00 9C00 9BFF
2
0x4000 003F 0x4000 0000 0x3FFF FFFF CONFIG. REGS
0x8003 0000 0x8002 FFFF
64B
0x8002 0000 0x8001 FFFF
B0F6(2)
64K
1
0x2000 000F 0x2000 0000 0x1FFF FFFF NATIVE ARBITER
B0F5(3)
64K
0xFFFF 9800 0xFFFF 97FF
reserved
0xFFFF 9400 0xFFFF 93FF
16B
0x8001 0000 0x8000 FFFF
0xFFFF 9000 0xFFFF 8FFF
reserved reserved I C1 I2C 0 APB BRIDGE 0 REGS
2
B0F4
0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 8000 7FFF 6000 5FFF 4000 3FFF 2000 1FFF 0000
32K 8K 8K 8K 8K
0xFFFF 8C00 0xFFFF 8BFF 0xFFFF 8800 0xFFFF 87FF 0xFFFF 8400 0xFFFF 83FF 0xFFFF 8000
0
0x0010 0017 0x0000 0000 FLASH (1)
B0F3 B0F2 B0F1 B0TF
64K/128K/256K
(1) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes) (2) Only available in STR73xZ2/V2 (3) Only available in STR73xZ2/V2 and STR73xZ1/V1 (4) Only available in STR730/STR731
Drawing not to scale access to gray shaded area will return an ABORT
20/22
STR73xF Data Brief
2 ORDER CODES
Table 4. Order Codes
Partnumber STR730FZ1T7 STR730FZ2T7 STR730FZ1H7 STR730FZ2H7 STR735FZ1T7 STR735FZ2T7 STR735FZ1H7 STR735FZ2H7 STR731FV0T7 STR731FV1T7 STR731FV2T7 STR736FV0T7 STR736FV1T7 STR736FV2T7 FLASH Kbytes 128 256 128 256 128 256 128 256 64 128 256 64 128 256 Package TQFP144 20x20 LFBGA144 10x10 TQFP144 20x20 LFBGA144 10x10 TQFP100 14x14 6 TQFP100 14x14 0 16 3 12 18 72 TIM CAN RAM Kbytes Timers Periph. A/D Chan. Wake-up Lines I/O Ports Temp. Range
3 10 0 -40 to +105C 16 32 112
21/22
STR73xF Data Brief Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
22/22

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